There has been a conventional method for selecting defective parts in CMOS semiconductor integrated circuit devices. Generally, the method is well-known as the IDDQ test, which measures the supply current (IDD) of respective semiconductor integrated circuits set in the quiescent state. This IDDQ test makes good use of the characteristics of the CMOS semiconductor integrated circuits; concretely no current flows in the quiescent state and a leakage current flows only in defects of the circuits.
Although the IDDQ test is effective to detect defects in this manner, current measurement takes more time than voltage measurement and such an increase of the testing time causes a problem of cost increase. Japanese Patent Laid-open (Kokai) No. Hei 6-58981 discloses a method for solving this problem by converting a supply current to a voltage via a resistor. The converted voltage is then amplified and a signal denoting reliable/defect is output according to this voltage value.
In recent years, along with the shrinkage of CMOS semiconductor integrated circuits, the break-down voltage, as well as the supply voltages of transistors have been reduced. In addition, along with the supply voltage becoming lower, the threshold voltages of those transistors must also be lowered.
When a threshold voltage of a transistor is kept high, the supply voltage, which is one of the two signal levels, comes up to the threshold voltage, so that signal distinguishing becomes difficult. In order to avoid such a problem, therefore, the threshold voltage is lowered to make a difference sufficiently between one of the signal levels and the threshold voltage.
On the other hand, when the threshold voltage is lowered, the ground level, which is the other level of the signal, comes up to the threshold voltage. Generally, only a slight current flows in a transistor with respect to the applied voltage until the threshold voltage is reached. When the threshold voltage is exceeded, the full current begins flowing suddenly in the transistor. However, this slight current becomes a leakage current and this leakage current increases as the applied voltage comes up to the threshold voltage. In other words, the transistor is characterized by the leakage current increasing proportionally to the falling of the threshold voltage.
In the case of MOS transistors, because the gate oxide film are becoming thinner, tunnel current has increased. This tendency also generates a leakage current. A leakage current caused by both of this tunnel current and the above-described falling of the threshold voltage increases along with the shrinkage of the MOS transistors, so that a considerable amount of leakage current comes to flow in the subject CMOS semiconductor integrated circuit even in the quiescent state. The characteristics of such the leakage current are different from those of the leakage current flowing only in defects described above. Hereinafter, therefore, this leakage current will be referred to as the normal leakage current.
Generally, it cannot be avoided that the normal leakage current is varied due to the fabrication process variation. When a leakage current increases due to a shrinking process, the variation is widened. Consequently, the normal leakage current differs even among normal chips sometimes when a leakage current from a supply current is measured. For example, while the supply current of a chip becomes 10 μA, the supply current of another chip designed in the same way as the above chip becomes 100 μA.
In the case of the IDDQ test, a current increase to be caused by a defect is expected to be about 100 μA. Consequently, when the supply current of a measured chip is 100 μA, it is difficult to decide whether it is caused by a defect or it is the normal leakage current caused by the fabrication process variation.
Although the conventional technique can perform the IDDQ test quickly, employment of the technique has not been expected for the measurement of CMOS semiconductor integrated circuits developed in recent years, in which the normal leakage current increases as described above. In other words, the above conventional technique cannot distinguish between a leakage current caused by a defect and the normal leakage current.
Under such circumstances, it is an object of the present invention to provide a semiconductor integrated circuit device provided with means enabled to perform the IDDQ test quickly when the leakage current increases due to the shrinkage of CMOS semiconductor integrated circuits.